1. Field of the Invention
The present invention relates to a voltage generation device, and more particularly to a voltage generation device for generating a voltage to be applied to a gate portion of a MOS transistor when performing a reset by transferring a charge which is stored in a source portion to a drain portion of the MOS transistor.
2. Description of the Background Art
In the upper half of FIG. 10 is shown a conventional structure of a part of a horizontal transfer register (HCCD) of a CCD solid-state imaging device, as well as a charge detection section for detecting a signal charge having been transferred from the HCCD. The lower half of FIG. 10 shows potentials of the respective portions in the HCCD and the charge detection section. Hereinafter, the structure and operation of the conventional HCCD and charge detection section will be briefly described.
The HCCD includes electrodes 1001 to 1003. The electrode 1001 is a transfer gate electrode, to which a clock voltage φH1 is applied. The electrodes 1002 and 1003 are transfer gate electrodes, to which a clock voltage φH2 is applied. The clock voltages φH1 and φH2 have the same clock frequency, but are opposite in phase. The clock voltages φH1 and φH2 applied to these electrodes create a potential difference of φh within the HCCD. Due to this potential difference φh, the signal charge is transferred from the left to right in FIG. 10.
The charge detection section comprises an electrode 1004, a source portion 1005, a reset gate portion 1006, a drain portion 1007, a channel portion 1008, and an amplifier 1009. A voltage VOG is applied to the electrode 1004. The signal charge 1010 which has been transferred from the HCCD is stored in the source portion 1005. The source portion 1005 is connected to the amplifier 1009. The amplifier 1009 converts the signal charge 1010 to a voltage, and outputs the voltage to outside of the charge detection section.
In order to perform a reset by draining the signal charge 1010 stored in the source portion 1005 to the drain portion 1007, a bias voltage Vb and a clock voltage φR as shown in FIG. 11 are applied to the reset gate portion 1006. The channel portion 1008 previously has a channel potential φch. The potential of the channel portion 1008 is increased by φb with the bias voltage Vb being applied to the gate electrode, and varies by φcl due to the clock voltage φR.
A predetermined voltage VRD is applied to the drain portion 1007 in order to drain out the signal charge which comes in from the source portion 1005 by the action of the reset gate portion 1006.
Now, the operation of the conventional charge detection section having the above structure will be described with reference to the figures. FIG. 12 is a diagram illustrating the potentials of the respective portions when the pulse voltage φR is applied to the reset gate portion 1006 of the conventional charge detection section.
As shown in FIG. 12, when the pulse voltage φR is applied to the reset gate portion 1006, the channel portion 1008 has a potential of φch+φb+φcl, which is higher than the potential VRD of the drain portion 1007. As a result of this, as shown in FIG. 12, the signal charge 1010 stored in the source portion 1005 is drained to the drain portion 1007, whereby the charge detection section is reset.
The potential VRD and the pulse voltage φR, which are to be generated within an apparatus which incorporates the charge detection section, vary from apparatus to apparatus. Therefore, for example, if the potential VRD takes its maximum value and the pulse voltage φR takes its minimum value under given operating conditions of the apparatus, the potential φch+φb+φcl of the channel portion 1008 will have a smaller value than that of the potential VRD of the drain portion 1007, as shown in FIG. 13. As a result, the charge detection section suffers from what is called a sub-threshold state in the field of MOS transistors, resulting in a reset residue 3000. Thus, a proper reset is not performed in the charge detection section.
Therefore, in order to prevent the above problem, a relatively large value is chosen for the bias voltage Vb to be applied to the reset gate portion 1006. As described in Japanese Patent Laid-Open Publication No. 2002-231889, for example, the bias voltage Vb having a relatively large prescribed value, may be stored in a storage section in a voltage generation circuit, which in itself is an external element connected to the charge detection section. The voltage generation circuit applies the bias voltage Vb stored in its storage section to the reset gate portion 1006. In this manner, the aforementioned sub-threshold state can be prevented from occurring in the MOS transistor structure.
However, if the value of the bias voltage Vb is too large, as shown in FIG. 14, the reset gate portion 1006 will have an excessively high potential even when the pulse voltage φR is not applied thereto. As a result, a saturation-decrease signal charge 4000 occurs, thus deteriorating the saturation characteristics. Thus, in the conventional charge detection section, it is difficult to prescribe the value of the bias voltage Vb to be applied to the reset gate portion 1006.